Architectures for Silicon Nanoelectronics and Beyond

R. Iris Bahar, Brown University Clifford Lau, Institute for Defense Analyses
Dan Hammerstrom, Portland State University Diana Marculescu, Carnegie Mellon University
Justin Harlow, University of South Florida Alex Orailoglu, University of California, San Diego
William H. Joyner Jr., Semiconductor Research Corp. Massoud Pedram, University of Southern California

The semiconductor industry faces serious problems with power density, interconnect scaling, defects and variability, performance and density overkill, design complexity, and memory-bandwidth limitations. Instead of raw clock speed, parallelism must now fuel further performance improvements, while few persuasive parallel applications yet exist.

A candidate to replace complementary metal-oxide semiconductor (CMOS) technology, nanoelectronics could address some of these challenges, but it also introduces new problems. Molecular-scale computing will likely allow additional orders-of-magnitude improvements in device density and complexity, which raises three critical questions:

• How will we use these huge numbers of devices?
• How must we modify and improve design tools and methodologies to accommodate radical new ways of computing?
• Can we produce reliable, predictable systems from unreliable components with unpredictable behavior?

The effective use of nanotechnology will require not just solutions to increased density, but total system solutions. We can’t develop an architecture without a sense of the applications it will execute. And any paradigm shift in applications and architecture will have a profound effect on the design process and tools required. Researchers must emphasize the complementary architectural and system issues involved in deploying these new technologies and push for greater collaboration at all levels: devices, circuits, architecture, and systems.

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